Now, I am using the srio_v5_6 Ip core in the ISE13.1 software. I use the CORE generator generate a srio_v5_6 IP core for the X6VLX240T-1156-1device.
Then I use the ISE13.1 software open the "srio_v5_6.xise". And I synthesize the project and Implement the it, but errors happen when implement the project as follow:
ERROR:NgdBuild:604 - logical block 'srio_icon_gen.i_srio_icon' with type
'srio_icon' could not be resolved. A pin name misspelling can cause this, a
missing edif or ngc file, case mismatch between the block name and the edif
or ngc file name, or the misspelling of a type name. Symbol 'srio_icon' is
not supported in target 'virtex6'.
ERROR:NgdBuild:604 - logical block 'rio_de_wrapper/rio_ila1_gen.i_rio_ila' with
type 'rio_ila' could not be resolved. A pin name misspelling can cause this,
a missing edif or ngc file, case mismatch between the block name and the edif
or ngc file name, or the misspelling of a type name. Symbol 'rio_ila' is not
supported in target 'virtex6'.
ERROR:NgdBuild:604 - logical block
'rio_de_wrapper/phy_wrapper/srio_ila2_gen.i_phy_ila' with type 'phy_ila'
could not be resolved. A pin name misspelling can cause this, a missing edif
or ngc file, case mismatch between the block name and the edif or ngc file
name, or the misspelling of a type name. Symbol 'phy_ila' is not supported in
target 'virtex6'.
ERROR:NgdBuild:604 - logical block
'user_top/initiator_user/tickler/srio_vio_gen.i_srio_vio' with type
'srio_vio' could not be resolved. A pin name misspelling can cause this, a
missing edif or ngc file, case mismatch between the block name and the edif
or ngc file name, or the misspelling of a type name. Symbol 'srio_vio' is not
supported in target 'virtex6'.
What's wrong with it? Can you help me ?
Thank you very much!
